Abstract

VILLA-ANGULO, C. et al. Implementation of a 10.24 GS/s 12-bit Optoelectronics Analog-to-Digital Converter Based on a Polyphase Demultiplexing Architecture. J. appl. res. technol [online]. 2013, vol.11, n.1, pp.115-123. ISSN 2448-6736.

In this paper we present the practical implementation of a high-speed polyphase sampling and demultiplexing architecture for optoelectronics analog-to-digital converters (OADCs). The architecture consists of a one-stage divideby-eight decimator circuit where optically-triggered samplers are cascaded to sample an analog input signal, and demultiplex different phases of the sampled signal to yield low data rate for electronic quantization. Electrical-in to electrical-out data format is maintained through the sampling, demultiplexing and quantization processes of the architecture thereby avoiding the need for electrical-to-optical and optical-to-electrical signal conversions. We experimentally demonstrate a 10.24 giga samples per second (GS/s), 12-bit resolution OADC system comprising the optically-triggered sampling circuits integrated with commercial electronic quantizers. Measurements performed on the OADC yielded an effective bit resolution (ENOB) of 10.3 bits, spurious free dynamic range (SFDR) of -32 dB and signal-to-noise and distortion ratio (SNDR) of 63.7 dB.

Keywords : optoelectronics analog-to-digital converter (ADC); poly-phase conversion scheme; self-synchronized sampling; demultiplexing process.

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