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Journal of applied research and technology
versión On-line ISSN 2448-6736versión impresa ISSN 1665-6423
J. appl. res. technol vol.2 no.2 Ciudad de México ago. 2004
Performance of a new bus assignment algorithm for an ATM switch fabric
J. Sánchez1, D. Torres2, E. Ruiz1 & M. Guzmán2
1 CICESE, Depto. de Electrónica y Telecomunicaciones, Km. 107 Carretera Tijuana-Ensenada, Ensenada, B.C., 22860, México. Tel:(646)1744502-06, Fax: (646)1750554, e-mail: jasan@cicese.mx
2 Centro de Investigación y de Estudios Avanzados del IPN, Unidad Guadalajara, Prol. López Mateos Sur 590, Guadalajara, Jal., México.
Received: May 24th, 2002.
Accepted: February 19th, 2003.
Abstract
This paper presents the results of the performance evaluation, through analytical and simulation models, of a High Speed Packet Switch with a New Bus Assignment Algorithm, designed and developed at the Research and Advanced Studies Center of National Polytechnic Institute in Guadalajara, México (CINVESTAV-GDL). The analytical model is tested under two different arrival processes: Binomial and Poisson distributions. The simulation model is tested with two bus assignment algorithms: Fixed Start and Rotated Start . The performance parameters considered are: Cell Loss Rate, Delay and Throughput.
Keywords: ATM Switch, Bus assignment algorithm, Cell loss rate, Poison arrivals, Throughput.
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