Resumen

CASTILLO-SORIA, F.R.; PACHECO-BAUTISTA, D.  y  SANCHEZ-MERAZ, M.. Frame, bit and chip error rate evaluation for a DSSS communication system. Ing. invest. y tecnol. [online]. 2008, vol.9, n.3, pp.271-277. ISSN 2594-0732.

The relation between chips, bits and frames error rates in the Additive White Gaussian Noise (AWGN) channel for a Direct Sequence Spread Spectrum (DSSS) system, in Multiple Access Interference (MAI) conditions is evaluated. A simple error-correction code (ECC ) for the Frame Error Rate (FER) evaluation is used. 64 bits (chips) Pseudo Noise (PN) sequences are employed for the spread spectrum transmission. An iterative Montecarlo (stochastic) simulation is used to evaluate how many errors on chips are introduced for channel effects and how they are related to the bit errors. It can be observed how the bit errors may eventually cause a frame error, i. e. CODEC or communication error. These results are useful for academics, engineers, or professionals alike.

Palabras llave : simulation; spread spectrum; multiple access; frame error rate.

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