Investigación

 

Electrical characterization of planarized a-SiGe:H Thin-film Transistors

 

M. Dominguez^a,b, P. Rosales^a and A. Torres^a

 

^a National Institute for Astrophysics, Optics and Electronics (INAOE), Electronics Department, Luis Enrique Erro No. 1, Puebla, Z.P. 72840, Mexico.

^b Department of Materials Science & Engineering, The University of Texas at Dallas, Richardson, TX 75080, USA. Tel: (52)(222) 266-3100 Fax: (52)(222) 247-0517. e-mail: mdominguez@inaoep.mx

 

Recibido el 25 de julio de 2012
Aceptado el 22 de octubre de 2012

 

Abstract

In this work the electrical characterization of n-channel a-SiGe:H TFTs with planarized gate electrode is presented. The planarized a-SiGe:H TFTs were fabricated at 200°C on corning glass substrate. The devices exhibit a subthreshold slope of 0.56 V/Decade, an on/off-current ratio approximately of 10⁶ and off-current approximately of 0.3 × 10^-12 A. The results show an improvement of the electrical characteristics when are compared to those unplanarized devices fabricated at higher temperature. Moreover, the simulation of the device using a SPICE model is presented.

Keywords: Thin-film transistor; hydrogenated amorphous silicon-germanium; low-temperature; spin-on glass; spice.

 

PACS: 81.05.Gc; 81.15.Gh; 85.30.Tv

 

DESCARGAR ARTÍCULO EN FORMATO PDF

 

Acknowledgments

The authors want to thank to all personnel of the laboratory of microelectronics at INAOE and to the CONACYT for the scholarship No. 160547.

 

References

1. G. Lucovsky and J. Phillips, Mater. Res. Soc. Symp. Proc. 558 (2000) 135.         [ Links ]

2. Y. Kuo, Thin-film transistors, materials and processes Vol. 1, (Kluwer academic publishers, Boston MA, 2004). p.p. 241–271.         [ Links ]

3. M. Meitine and A. Sazonov, Mater. Res. Soc. Symp. Proc. 769 (2003) H6.6.         [ Links ]

4. M. Dominguez, P. Rosales, A. Torres, M. Moreno, and A. Orduña, Thin Solid Films 520 (2012) 5018.         [ Links ]

5. P. Rosales, A. Torres, R. Murphy, F. J. De la Hidalga, L. F. Marsal, R. Cabre, and J. Pallarès, J. Appl. Phys., 97 (2005) 8.         [ Links ]

6. M. Dominguez et al, Superficies y Vacio 24 (2011) 1.         [ Links ]

7. C. Lee, D. Striakhilev, S. Tao and A. Nathan, IEEE Electron Device Lett. 26 (2005) 637.         [ Links ]

8. K. Long, A. Kattamis, I. Cheng, H. Gleskova, S. Wagner and J. Sturm, IEEE Electron Device Lett. 27 (2006) 111.         [ Links ]

9. J. Cheon, J. Bae and J. Jang, IEEE Electron Device Lett. 29 (2008) 235.         [ Links ]

10. M. Powell, IEEE Trans. Electron Devices 36 (1989) 2753.         [ Links ]

11 . B. Wu, C. Hao, T. Wu, M. Chen, M. Jow and H. Chen, IEEE Trans. Electron. Devices 36 (1989) 2903.         [ Links ]

12. M. Shur, H. Slade, M. Jacunski, A. Owusu and T. Ytterdal, J. Electrochem. Soc. 144 (1997) 2833.         [ Links ]

13. http://www.aimspice.com/.         [ Links ]

14. M. Shur et al, Mater. Res. Soc. Symp. Proc. 467 (1997) 831.         [ Links ]