A New Design Methodology for Composing Complex Digital Systems

 

S. L. Chu*¹, M. J. Lo²

 

¹ Department of Information and Computer Engineering Chung Yuan Christian University Chung Li, 32023, Taiwan. *slchu@cycu.edu.tw.

² Department of Information and Computer Engineering Chung Yuan Christian University Chung Li, 32023, Taiwan.

 

ABSTRACT

Continuous growth in the use of multimedia applications on portable devices makes the mobile computer systems have an increasing complexity. The functionalities of the used SOC chips and silicon intelligent properties in these portable devices are become complicated and hard to design. Traditional digital circuit designs adopt register transfer level with timing control methodologies, which focus on the datapath composition, timing control of registers, and the functions of combinational circuits. However, the huge amount of control and synchronous signals of the above components are difficult to design and debug. The timing costs of design and verification are increased dramatically. This paper proposed a new design methodology of digital system, called data-oriented methodology, to deal with the above problems, by using Bluespec SystemVerilog HDL and the corresponding tools. Instead of conventional timing-control mechanism, the data-oriented methodology adopts simple handshaking protocol, blocking transferring, and explicitly register/FIFO declaration for communicating between adjacent modules. The designs of FDCT/IDCT and pipelined MIPS-like CPU are adopted to compare the design costs of conventional timing-control and data-oriented methodologies. The chip performance and FPGA proven of these two designs are discussed.

Keywords: SOC, Bluespec SystemVerilog, data-oriented methodology, IDCT/FDCT, MIPS-like processor.

 

DESCARGAR ARTÍCULO EN FORMATO PDF

 

Acknowledgements

This work is supported in part by the National Science Council of Republic of China, Taiwan under Grant NSC 101-2221-E-033-049.

 

References

[1] S. Gupta et al., "SPARK: a High-Level Synthesis Framework for Applying Parallelizing Compiler Transformations," in International Conference of VLSI Design, 2003, pp. 461-466.         [ Links ]

[2] Bluespec Inc., Bluespec SystemVerilog Reference Guide, Available from: http://www.bluespec.com.         [ Links ]

[3] A. Benvensitee et al., "The Synchronous Languages 12 Years Later," Proceedings of the IEEE, vol. 91, no. 1, pp. 64-93, 2003.         [ Links ]

[4] Arvind, and X. Shen, "Using Term Rewriting Systems to Design and Verify Processors," IEEE Micro, vol. 19, no. 3, pp. 36-46, 1999.         [ Links ]

[5] W. H. Chen et al., "A Fast Computational Algorithm for the Discrete Cosine Transform," IEEE Trans. on Communication, vol. 25, no. 9, pp. 1004-1009, 1977.         [ Links ]

[6] D. A. Patterson, and J. L. Hennessy, Computer Organization & Design: The Hardware/Software Interface, 4th ed., Morgan Kaufmann, 2009.         [ Links ]

[7] J. Plosila, and K. Sere, "Action Systems in Pipelined Processor Design," in Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1997, pp. 156-166.         [ Links ]

[8] S. L. Chu, and C. C. Hsiao, "Golden-Finger and Back-Door: Two HW/SW Mechanisms for Accelerating Multicore Computer Systems," International Journal of Engineering and Technology Innovation, vol. 2, no. 1, pp. 72-84, 2012.         [ Links ]

[9] A. Dargužis et al., "Dynamic Processes of a Vehicle Moving over Stepshaped Obstacles," Journal of Vibroengineering, vol. 13, no. 3, 2011.         [ Links ]

[10] A. Khalkhali et al., "Modeling and Multi-Objective Optimization of Forward-Curved Blade Centrifugal Fans Using CFD and Neural Networks," Transactions of the Canadian Society for Mechanical Engineering, vol. 35, no. 1, pp. 63-79, 2011.         [ Links ]

[11] ARM Inc., Integrator Logic Module User Guide. Available from: http://www.arm.com.         [ Links ]

[12] A. Sangiovanni-Vincentelli, and "Vadis Quo, SLD? Reasoning about the Trends and Challenges of System Level Design," Proceedings of the IEEE, vol. 95, no. 3, pp. 467-506, 2007.         [ Links ]

[13] G. Stehr, and J. Eckmüller , "Transaction Level Modeling in Practice: Motivation and Introduction," in International Conference on Computer-Aided Design, 2010, pp. 324-331.         [ Links ]

[14] R.A. Bergamaschi, "Bridging the Domains of High-Level and Logic Synthesis," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 5, pp. 582-596, 2002.         [ Links ]

[15] R. A. Bergamaschi, and S. Raje, "Control-Flow versus Data-Flow-Based Scheduling: Combining Both Approaches in An Adaptive Scheduling System," IEEE Trans. on Very Large Scale Integration System, vol. 5, no. 1, pp. 82-100, 1997.         [ Links ]

[16] A. Orailoglu, and D. D. Gajski, "Flow Graph Representation," in 23rd ACM/IEEE Design Automation Conference, 1986, pp. 503-509.         [ Links ]

[17] J. Keinert et al., "SystemCoDesigner - An Automatic ESL Synthesis Approach by Design Space Exploration and Behavioral Synthesis for Streaming Applications," ACM Trans. on Design Automation of Electronic Systems, vol. 14, no. 1 pp. 1-23, 2009.         [ Links ]

[18] E. A. Lee et al., "Actor-Oriented Design of Embedded Hardware and Software Systems," Journal of Circuits, Systems and Computers, vol. 12, no. 03, pp. 231-260, 2003.         [ Links ]

[19] Forte Design Systems. Available from: http://www.forteds.com.         [ Links ]

[20] T. Grotker et al., System Design with SystemC, Kluwer Academic Publishers, 2002.         [ Links ]

[21] Mentor Graphics Corp., Available from: http://www.mentor.com.         [ Links ]

[22] NEC System Technologies, Ltd., Available from: http://www.cyberworkbench.com.         [ Links ]